The invention relates to a decoding apparatus for transmitting a high voltage signal.
In the fields of microelectronics, information technology, and the like, it is often necessary to code and/or decode a multiplicity of addresses for electronic components in hardware. Such coding/decoding is performed in order to address memory elements, sensor elements, e.g., in image sensors, actuator elements, or the like, and, consequently, to call up their contents in order to read them, change their state, or the like.
In particular, in the case of memory chips, such as DRAMs, it is customary to select individual word lines from predecoded addresses in a word line decoder. In such a context, in prior art decoding apparatuses, in particular, for transmitting high voltage signals, a final decoder is provided for the switchable transmission of a transmission signal. In addition, a transmission signal line device is configured to supply the transmission signal to the final decoder, and a driver signal line device is configured to supply a driver signal to the final decoder. Also, an output signal line device is configured to output an output signal from the final decoder. The final decoder has a first switching device, with at least one field effect transistor as the switching element. In these prior art decoding apparatuses, the gate line of the respective field effect transistor can have the driver signal applied to it, and the respective source line can have the transmission signal applied to it, specifically such that, when the driver signal is resetxe2x80x94e.g., from high to low, the output signal can be connected to the output signal line device and appears there.
Thus, the effect achieved in the prior art decoding apparatus is that a high voltage output signal appears at the output of the final decoder if the corresponding driver signal on the gate line changes from high to low.
There is a disadvantageous aspect of the construction of these prior art decoding apparatuses, particularly when high voltage signals are being transmitted, because particular circumstances do not allow the temporal relationship, that is to say, in particular, the time interval, between the high/low change of the driver signal and the low/high change of the transmission signal to be observed. Such observation is not allowed because, if the driver signal changes to low while the output signal is already rising or has already risen, the output characteristic curve of the appropriate field effect transistor would be traversed from the saturation region to the resistance region, that is to say under load. In such a context, however, high channel voltages in the transmission channel may arise in the saturation region, and, consequently, there is a high likelihood that the line channel of the transistor will be degraded. The channel degradation is based to a considerable extent on the fact that hot electrons at the semiconductor/insulator interface, in particular, the Si/SiO2 interface, cause faults. These faults can result in the threshold voltage being shifted and in the channel mobility being reduced. Degradation of the transistor and its consequential phenomena increase the likelihood of a permanent change in the transistor properties and in its switching response, and the likelihood of failure also increases. Hence, there is also the possibility of damage to the component, to the memory chip, or the like.
It is accordingly an object of the invention to provide a decoding apparatus that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and in which the likelihood of damage and of failure when high voltage signals are being transmitted is particularly small.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a decoding apparatus for transmitting a high voltage signal, including a final decoder for switchably transmitting a transmission signal, the final decoder having a switching device, a transmission signal line device configured to supply the transmission signal to the final decoder, a driver signal line device configured to supply a driver signal to the final decoder, and an output signal line device configured to output an output signal from the final decoder, the switching device having at least one field effect transistor with a gate line, a source line, and an output, the at least one field effect transistor having a low threshold voltage, the driver signal line device connected to the gate line for applying the driver signal to the gate line, the transmission signal line device connected to the source line for applying the transmission signal to the source line, the output signal line device selectively connected to the output, and the at least one field effect transistor configured to selectively connect the output signal to the output signal line device through the output in response to a reset of the driver signal.
The first way in which the invention achieves its objectives is for the field effect transistor in the first switching device of the final decoder to be respectively constructed to have a low threshold voltage, to wit, between 0.1 and 0.4 volts. The effect achieved by the low threshold voltage is that, when the driver signal changes from high to low, the field effect transistor is actually taken as early as possible, i.e., without any load, from the saturation region into the resistance region, so that the smallest possible time overlap between the high/low change in the driver signal and the low/high change in the transmission signal results. Therefore, the likelihood of channel degradation is reduced.
In such a case, it is particularly advantageous that the respective field effect transistor in the first switching device of the final decoder is a low VT field effect transistor.
With the objects of the invention in view, there is also provided a decoding apparatus for transmitting a high voltage signal, including a final decoder for switchably transmitting a transmission signal, the final decoder having a switching device, a transmission signal line device configured to supply the transmission signal to the final decoder, a driver signal line device configured to supply a driver signal to the final decoder, and an output signal line device configured to output an output signal from the final decoder, the switching device having at least one depletion-mode-type field effect transistor with a gate line, a source line, and an output, the driver signal line device connected to the gate line for applying the driver signal to the gate line, the transmission signal line device connected to the source line for applying the transmission signal to the source line, the output signal line device selectively connected to the output, and the at least one field effect transistor configured to selectively connect the output signal to the output signal line device through the output in response to a reset of the driver signal.
In accordance with a further way in which the invention achieves the object, provision is made for the field effect transistor in the first switching device of the final decoder to be respectively a depletion mode field effect transistor, in particular, a depletion mode PFET. The configuration likewise increases the likelihood that, in the event of a time overlap between a falling driver signal and a rising transmission signal, the transistor operates in the resistance region, and, therefore, outside the saturation region, at an earlier instant. As a result, the time overlap and, hence, the likelihood of channel degradation are reduced. Preferably, the depletion mode type field effect transistor has a low threshold voltage, preferably, between 0.1 and 0.4 volts. In particular, the depletion mode field effect transistor is a normally-on, depletion mode field effect transistor.
It can be regarded as a further advantage that the field effect transistor in the first switching device of the final decoder is respectively configured as a field effect transistor of the depletion mode type having a low threshold voltage, i.e., between 0.1 and 0.4 V. The configuration also ensures that the field effect transistor switches early so that it operates in the resistance region as soon as possible, further reducing the likelihood of channel degradation as a result of operation in the saturation region under load.
Both of the invention""s ways of achieving its objectives have the additional advantage thatxe2x80x94particularly in the case of the depletion mode PFETxe2x80x94the current yield is increased. Increasing the current yield means that the respective field effect transistor can be smaller or have smaller proportions, which, in particular, also becomes noticeable in the fact that the transistor in question has a smaller physical size. The reduction becomes clear, in particular, when one considers that a multiplicity of homogeneous switching transistors need to be produced on one memory chip, for example, in a corresponding decoding apparatus.
In accordance with another feature of the invention, the respective field effect transistor in the first switching device of the final decoder is a p-channel-conductive field effect transistor, and, preferably, is a normally-on-type p-channel-conductive field effect transistor.
In accordance with a further feature of the invention, there is provided a driver device that generates the driver signal and outputs it on the driver signal line device. Such a configuration ensures that the data supplied to the decoding apparatus permits a driver signal for selecting and calling up the appropriate word line to output the independently generated output signal.
In accordance with an added feature of the invention, there is provided a predecoder configured to receive and predecode a supplied address signal and to generate and supply a driver control signal to the driver signal line device.
Such a context provides a particular advantage. An appropriate predecoder is produced that is configured to receive and predecode a supplied address signal and to generate and supply a driver control signal, in particular, to the driver device. Thus, the supplied addresses are evaluated in advance by predecoding. In addition, to control the driver device, an appropriate driver control signal is generated and is output to the driver device.
In accordance with an additional feature of the invention, there is provided a reset signal line device that is configured to supply a reset signal to the final decoder.
In accordance with yet another feature of the invention, there is provided a second switching devicexe2x80x94in particular in the final decoderxe2x80x94that can reset the output signal line device, in particular, to a zero potential.
The effect achieved is that the output signal line device or a component thereof is set to a defined potential in response to the reset signal being supplied, so that, in particular, no output signal at all appears on the output signal line device or on an individual line or component thereof. Consequently, the reset signal can disconnect the output signal line device or a component thereof in a defined manner.
To such an end, in one preferred embodiment, the second switching device has a field effect transistor whose gate line is configured to receive the reset signal and whose source line is configured for connection to the output signal line device or a component thereof.
The embodiments described hitherto characterize the fundamental configuration of the proposed decoding apparatus for transmitting a high voltage signal. The measures discussed above are particularly advantageous due to the fact that, in memory chips or the like, for example, the proposed measures are adopted or produced with a high level of multiplicity, because the corresponding line devices have a multiplicity of individual line components or individual lines having corresponding individual addresses or individual address signals. Consequently, for a plurality of individual lines, corresponding switching elements in the form of essentially identical field effect transistors also need to be produced.
Accordingly, in one preferred embodiment of the decoding apparatus according to the invention, the transmission signal line device, the output signal line device, and the driver signal line device each have a plurality of individual lines, namely transmission signal lines, output signal lines, and driver signal lines, for the parallel transmission of a respective signal component. In addition, the first switching device has a corresponding plurality of field effect transistors, in particular, normally-on, field effect transistors, a respective gate line of a particular field effect transistor is connected to a respective driver signal line, and a respective source line of the particular field effect transistor is connected to a respective transmission signal line, in order to transmit a respective component of the output signal such that it can be connected to an output signal line in parallel.
Due to the multiplicity of the line devices and of the switching elements, a concomitant feature of the invention provides for the reset signal line device to have a corresponding plurality of reset signal lines for supplying reset signal components, and for the second switching device to contain a corresponding plurality of field effect transistors for resetting the respective output signal lines.
The multiplicity of the second switching device and of the field effect transistors provided in it, in particular, further saves space. The depletion mode type field effect transistors are also able to transmit voltages in a region of 0 volts. Thus, the respective field effect transistor in the second switching devicexe2x80x94that is to say, the transistor for resetting the output signal linexe2x80x94can be reduced in size. Such reduction also results in a further saving of space.
Basic concepts of the decoding apparatus according to the invention are, thus, not to provide a conventional PMOS field effect transistor as a switching transistor, but to provide a respective field effect transistor having little likelihood of channel degradation when high voltage signals are transmitted, in particular, when there is a time overlap between the high/low change in the driver signal and the low/high change in the output signal. Such a configuration reduces the susceptibility to malfunctions and the likelihood of failure. In addition, the physical proportions of the field effect transistors in the first switching device and also in the second switching devices can be reduced, which results in space savings on the semiconductor modules.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a decoding apparatus, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.